[parisc-linux] Thoughts on arch/parisc/irq.c
Wed, 25 Aug 1999 19:13:04 -0700
Alan Cox wrote:
> > o Do GBD or other psuedo drivers need to reserve EIRR bits?
> > Ie soft interrupts to reschedule work at lower SPL levels.
> Linux has no notion of SPL levels at all. The model is
Alan - looks like something got dropped here. Try again?
> Hardware interrupt. These live in a unified space described by a cookie.
> We map the cookie to the irq number on a PC but that is optional. Drivers
> only know about irqs as a cookie.
I think there is going to a problem with "cookies" on PA.
The problem is GSC devices need to program an "EIM" register.
(For Dino, this is IAR0). The contents of the EIM register
are a processor HPA (bits 11-31) and EIRR bit number (bits 0-4;
ie a value 0-31). The location of this register is NOT
defined by PA I/O architecture - or at least not well defined.
Is this a real problem or not?
Another tidbit: I know of only one device which can use "6-bit"
(0-63) EIRR vectors. GSC and PCI devices which are capable of mastering
their own interrupt transactions can also use 6-bits. 6-bits is
obviously only supportable running a 64-bit kernel binary.
> Bottom half handlers. We invoke these on the path out of an irq before
> returning to the normal scheduled universe. mark_bh() sets a bh to be run
> on the next return. BH's are not run if they are already running - they
> are single threaded with respect to each other right now - that may change
> to be 'with respect to self' one day.
For single CPU is doesn't matter. For SMP scalability it might.
> Interrupts may occur during a bh, we normally dont allow interrupts during
> an IRQ handler on the same CPU.
SPL levels allow the system clock to always get service regardless of how
badly an ISR behaves on the interrupt stack. SPL levels also allow
the clock to "reschedule" work at a lower priority on the interrupt stack
to guarantee the timeout is called "pretty soon". SPL levels also
allow device drivers to service IRQs while the bottom half is active.
Allowing this nesting of SPL levels permits scheduling on the interrupt
stack. Any particular reason for not allowing this?
(eg abuse by driver writers)
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