Wed, 24 Nov 1999 15:24:32 -0800
Frank Rowand wrote:
> Philipp Rumpf wrote:
> > As soon as we've implemented page colouring (which turns out to be really v
> > close to large page support), I expect us to get along with very very few
> > cache flushes - basically I hope we can avoid them completely.
> > Philipp Rumpf
> No such luck. You'll need cache flushing in drivers for non-coherent IO.
Frank is (as usual) right. Rule of thumb is if the box doesn't have an
I/O MMU (aka ccio or sba) or not using it, then it's not I/O coherent.
Every DMA transaction will require flushes/purges before or after
(inbound vs. outbound) of payload and device control data on such boxes.
My understanding is only PA2.0 supports speculative prefetching.
AFIAK that's ok since all PA2.0 boxes have an I/O MMU and the prefetched
data will be recalled/dropped during the course of the DMA.
Conclusion: In the "performance code path", PA1.1 will generally (some
PA1.1 are also I/O coherent) need flushes/purges and PA2.0 won't.
However, I wouldn't code this based on PA2.0 vs PA1.1 since the presence
of U2/Uturn/sba are what matter. And we will probably want to ignore
those chips for PA2.0 bringup (ie bringup will be not be I/O coherent).
Unix Developement Lab