[parisc-linux] Re: Trap handler

Grant Grundler grundler@dsl2.external.hp.com
Mon, 9 Dec 2002 11:41:25 -0700

On Mon, Dec 09, 2002 at 06:20:33PM +0000, Matthew Wilcox wrote:
> On Mon, Dec 09, 2002 at 11:03:16AM -0700, Grant Grundler wrote:
> > > Judging from the use of cli & sti in the x86 asm, I would venture to
> > > suggest that the I bit should be cleared.  It makes sense anyway --
> > > you can't expect interrupts to be disabled over a page fault.
> i misremembered the sense of the I bit

As jsm agreed, if interrupts were disabled when we took the fault,
we can't re-enable them while handling a page fault.
Where x86 disables interrupts seems ok to me.

But the 2.4.20 parisc code (entry.S) re-enables interrupts at
intr_return label (ssm insn). Should parisc *not* be re-enabling
interrupts at all or at least not until after intr_check_resched
code block?

I'm trying to align x86/parisc implementations.
And "misaligned trap handler" is one difference I suspect
the x86 code doesn't have to handle.